Developments in cathode-ray tube (CRT), liquid crystal display (LCD), and plasma display panel (PDP) technology has been spurred in recent years by increasing demand for large screen televisions having high definition capabilities, an example of which is hi-vision.
CRTs, currently the most widely used type of display, exhibit excellent resolution and image quality characteristics, although the substantial increases in unit depth and weight that accompany increases in screen size make CRTs unsuitable for large-screen 40 inch plus applications. The advantage of LCDs, on the other hand, lies in their economical power usage and the consequent low drive voltages. There are, however, technical difficulties associated with enlarging the screen size of LCD displays, and also limitations concerning the viewing angle.
In comparison, PDPs are readily suitable for thin large-screen applications, and 40-inch class models have already been developed.
PDPs can be divided into AC-type and DC-type, the former currently considered the most suitable for large-screen applications. PDPs are also well suited for high-definition image display.
The general structure of known PDP technology is shown in FIGS. 1, 2 and 3. FIG. 1 is a perspective view of a main section of a prior art PDP. FIG. 2 shows a vertical cross-section of the main section along the X—X axis of FIG. 1. FIG. 3 shows a vertical cross-section of the main section along the Y—Y axis of FIG. 1.
A PDP is generally formed from a front panel PA1 and a back panel PA2, the two panels being affixed together around their respective peripheries. Front panel PA1 includes a first glass substrate 100. Plural pairs of display electrodes (first electrode 101a and second electrode 101b) are provided on substrate 100 so as to form a parallel stripe-pattern, one pair of which is shown in FIG. 1. A dielectric glass layer 102 composed of lead glass or the like is formed over the display electrodes. Layer 102 is covered with a magnesium oxide (MgO) protective layer 103 composed of an MgO evaporation film or the like.
Back panel PA2 includes a second glass substrate 110. A plurality of address electrodes (third electrodes 111) is provided in a parallel stripe-pattern on substrate 110. A dielectric glass layer 112 composed of lead glass or the like is formed over the third electrodes 111. A plurality of ribs 113 is arranged in a stripe-pattern on layer 112 so as to lie between and extend parallel to third electrodes 111. Phosphor layers 114 comprising the colors red (R), green (G), and blue (B), respectively, are formed between adjacent ribs 113.
Front panel PA1 and back panel PA2 are affixed together such that the first and second electrodes extend in an orthogonal direction to the third electrodes. A discharge gap composed of xenon, neon, argon, or the like, is enclosed in a space defined between the affixed front and back panels.
In the above structure, the first and second electrodes are arranged so as to define a discharge gap therebetween. The known PDP also includes a plurality of discharge cells CL, each cell CL being formed in a region where a single first electrode 101a and a single second electrode 101b extend across a single third electrode 111.
The following is a detailed description of a method for driving the known PDP, with reference to FIG. 4. The method used is a conventional field timesharing display method. The description relates to the driving of the known PDP in a single subfield. FIG. 4 shows drive waveforms pertaining to the subfield, “VX” denoting the amplitude of the various pulses. In FIG. 4, the ith line refers to the order in which the pair of electrodes in the line is scanned when data is written (i.e. addressed). The jth column, on the other hand, refers to the positioning of the third electrode 111 in relation to third electrodes in other columns.
As shown in FIG. 4 with respect to the first electrodes 101a, a positive initializing pulse (V1+V2) is applied in a first initializing period T1, and a positive initializing pulse V2 is applied in a second initializing period T2. With respect to the second electrodes 101b, a positive initializing pulse V2 is applied in the second initializing period T2, this pulse initializing a wall charge within the discharge cells CL.
In address period T3, a negative scan pulse V3 is applied to the ith line first electrode 101a and a positive address pulse V4 is applied to the jth column third electrode 111 corresponding to the discharge cell to be written (i.e. the cell positioned at an intersection of the ith line and the jth column).
As a result, an address discharge is generated between the first electrode 101a (ith line) and the address electrode 111 (jth column) in the cell in which the address pulse V4 was applied. This in turn initiates a surface discharge between the first and second electrodes in the ith line, wall charge being stored on the surface of dielectric layer 102 between the pair of electrodes subsequent to this discharge.
As a result of a continuous scanning of the first and third electrodes, increasing amounts of wall charge are stored on dielectric layer 102 in the discharge cells to be used for image display. It is this accumulation of wall charge that allows one screen of latent image to be written.
In a sustain period T4, the address electrodes are grounded and sustain pulses V5 are applied alternately to the first and second electrodes, thus generating a sustain discharge in the discharge cells having wall charge stored on dielectric layer 102. By weighting the illumination according to the number of sustain pulses applied in the period T4, it is possible to express gradations corresponding to the weights of the various sustain pulses.
In an erase period T5, an erase pulse V6 is applied to the second electrodes 101b, the amplitude of pulse V6 being substantially the same as that of pulse V5 and its duration being relatively short. A weak discharge is generated as a result, eliminating the wall charge, and thus erasing the latent image.
In the known PDP, one subfield of image display is generally conducted by consecutively performing the initializing period, the address period, the sustain period, and the erase period.
According to the prior art drive method described above, a potential of the first and second electrodes in the selected ith scan line is maintained at V0 and V2, respectively, in the address period. In other words, the potential V2 equals the voltage between the first and second electrodes in the discharge cell at the completion of the initializing period; that is, slightly lower than a discharge initiating voltage Vfs.
When address pulse V4 is applied to a third electrode 111, an address discharge occurs between the first and third electrodes, and priming particles are formed. The discharge initiating voltage Vfs between first and second electrodes decreases as a result of the priming particles, and a surface discharge is initiated between the first and second electrodes. Wall charge is stored as a result of the surface discharge, and a latent image is consequently written in the cells storing wall charge.
Also, the discharge initiating voltage Vfs applied between the first and second electrodes in cells that are in lines adjacent to the ith line (i.e. the already scanned i−1th line and the i+1th line to be scanned) is reduced when priming particles generated in the an ith line cell cross over into a cell in an adjacent line, this being a phenomenon that sometimes occurs.
Under normal circumstances, maintaining the potential of the first electrodes in the i−1th and i+1th lines at a positive voltage V3 allows the voltage occurring at the second electrodes in these respective lines to be established at a magnitude that is slightly lower than the discharge initiating voltage Vfs (when no priming has occurred) minus the voltage V3 (i.e. Vfs−V3). As a result, no address discharge is generated in cells that are in lines adjacent to the ith line.
However, when priming particles crossover into lines adjacent to the ith line, causing the discharge initiating voltage Vfs to decrease in the cells in these lines, there exists the possibility that an erroneous discharge will be initiated between the first and second electrodes in these cells in period T4. This erroneous display discharge occurs irrespective of whether the particular cells have been addressed or not, and is a phenomenon referred to as “crosstalk”. The elimination of crosstalk is one of the major tasks confronting PDP designer in their efforts toward improving image quality in PDPs.
The gravity of the problem is compounded by the fact that the frequency of crosstalk increases as cell size is reduced in high definition PDPs.